Practical Combinational Logic design3

1. Exclusive-OR and Parity circuits

1.1 Exclusive-OR Gates
Exclusive-OR (XOR) gate
2-input gate whose output is 1 if exactly one of its inputs is 1
Producing a 1 output if its inputs are different
X + Y = X´Y + XY´
(X + Y)´ = XY + X´Y´

Multigate design for 2-input XOR function (a) AND_OR (b) 3-level NAND

Equivalent symbols for (a) XOR gates (b) XNOR gates

Pinouts of 74x86 SSI XOR gate

1.1.2 XOR Gates in VHDL

3 input XOR Device [Dataflow Style]

1.2 Parity Circuits

Odd-parity circuits : cascading XOR gates (a) daisy-chain connection (b) tree structure

74x280 9-bit odd/even parity generator

1.3Error-Detection Circuits

8-bit bytes memory system (including 1 parity bit)

1.4 Hamming Codes (7 bits)
In a 7-bit message, there are seven possible single bit errors:
-> 3 error control bits could potentially specify
in which position the error occurs 4
-> 4 data bits, 3 parity bits

화살표 부분이 4 data bit

Error-Correcting Circuits for 7-bit Hamming code

1.4.2 

Hamming Error Correction [behavioral Style]

2. ALU(Arithmetic and Logic Unit)

2.1Comparators : Circuits to compare two binary words for equality

 

Comparing X(N-1)…X2X1X0 & Y(N-1)…Y2Y1Y0

CMP

EQI = 1 & X = Y → EQO = 1
EQI = 1 & X ≠ Y → EQO = 0
EQI = 0 → EQO = 0

2.1.1 74x85 4-bit Comparative IC

Comparing A3A2A1A0 & B3B2B1B0

AGTBOUT = (A>B) + (A=B)•AGTBIN
AEQBOUT = (A=B)•AEQBIN
ALTBOUT = (A<B) + (A+B)•ALTBIN
ALTBIN, AEQBIN, AGTBIN  → 1-out-of-3 code

2.1.2 12-bit Comparator Using 74x85

12-bit Comparator Using 74x85

2.1.3 74x682 8-bit Comparator

Comparing P7…P0 & Q7…Q0

(P > Q)
= P7Q7´ +
(P7 + Q7)´P6Q6´ +
(P7 + Q7)´(P6 + Q6)´P5Q5´ +
……

74x682 8-bit Comparator

2.2 Adders
2.2.1 Half Adders
Adding two 1-bit operands X and Y
Producing a 2-bit sum
LSB : HS (half sum) & MSB : CO (carry out)
HS = X + Y = XY´ + XY´
CO = XY

Half Adders

2.2.2 Full Adders
Adding operands with more than one bit

2.2.3 Ripple Adders ; Cascade of full adders

2.4 Carry lookahead adders

Slow because carry propagation
Worst-case total delay (n-bit adder)
-> Solution : Carry lookahead adders

Worst-case total delay

Solution : Carry lookahead adders

3. Substractors

3.1 Full Substractors
1-bit of the binary subtraction algorithm
D (difference) = X (minuend) – Y (subtrahend)
BIN : borrow in
BOUT : borrow out

 

 

ripple subtractor implemented by full adders

4. Carry Lookahead Adders
Eliminating carry ripple

 

 

4.1 74x283 Carry Lookahead Adder

74x283 Carry Lookahead Adder

74x283 Carry Lookahead Adder

74x283 Carry Lookahead Adder

 

74x283 Carry Lookahead Adder

16-bit Group-Ripple Adder

5. ALU (Arithmetic and Logic Units)
; Combinational circuit performing any of a number of different arithmetic and logical operations

Logic symbols for 4-bit ALUs

 

 

74x381 & 74x382 ALUs

6. Group-Carry Lookahead
- Multiple ALUs to be cascaded without ripple carry between 4-bit groups
- 16-bit ALU using group-carry lookahead

74x182 lookahead carry circuit

16-bit Adder using Group-Carry Lookahead

 

Adding and subtracting 8-bit integers of various types

Allowing adder sharing

7. Combinational Multipliers
- Shift & Add algorithm

partial products in 8x8 multiplier

7.1 Multiplication in VHDL

Behavioral VHDL program for 8x8 combinational multiplier