Practical Combinational Logic design2

1 .Decoders and Encoders

Decoder
A multiple-input, multiple-output logic circuit
Converting a coded input word into a coded output word
One-to-one mapping

1.1 Binary Decoders

n-bit input code and 1-out-of-2n output code
Used to activate exactly one of 2n outputs based on an n-bit
input value

3-to-8 binary decoder to decode a Gray code

1.2 Logic Symbols for Larger-Scale Elements
; General guidelines for drawing logic symbols for large-scale
elements

ex)
1.2.1 Such as 74-series MSI (medium-scale IC) decoders

1.2.2

74x139 dual 2 to 4 decoder

More ways to symbolize a 74x139

 

오른쪽 거는 신호가 중복되어서 잘못된 표기가 된다.

 

74 x 138 3 to 8 decoder

more ways to symbolize a 74 x 138

74 x 138 truth table

1.2.3 decoder 제작법 : cascading
- 74138 2개로 4 to 16 decoder 만들기
- 논리회로 카테고리에 같은 내용이 들어있다.

4 to 16 decoder

N3 = 0  → U1: enabled, U2: disabled
N3 = 1  → U1: disabled, U2: enabled

1.2.4

2 to 4 decoder VHDL code [Structural style]

3 to 8 decoder VHDL code [Dataflow style]

 One of better program styles
Not sufficient for maintenance of active low signals

Most VHDL programs are written almost entirely with active-high signals

 

hierachical definition of 74138

hierachical definition of 74138 => VHDL

hierachical definition of 74138 => VHDL

1.2.5

Behavioral style of VHDL program for 3-to-8 decoder

Easily adapted to make a binary decoder of any size

1.2.6 Seven-Segment Decoders

Seven-segment display and decimal digits

Input code → 4-bit BCD
Output code → “seven-segment code”
LED (light-emitting diode)
LCD (liquid-crystal display)

74x49 seven-segment decoder

truth table of 7 segment decoder

2. Encoders
A device’s output code has fewer bits than the input code
2n-to-n or binary encoder
Opposite function of a binary decoder

2.1

Priority Encoders

A system with 2n requestors : microprocessor input/output systems
A request encoder indicates which request signal is asserted at any time
Multiple requests can be made simultaneously
Ex.) I2 and I4 of the 8-to-3 encoder are both 1
→ Output is 110 → binary encoding = 6
→ undesirable result

I7 : the highest priority
H7 = I7
H6 = I6 I7´
H5 = I5 I6´ I7´
…
H0 = I0 I1´ I2´ I3´ I4´ I5´ I6´ I7´
A0 = H1 + H3 + H5 +H7
A1 = H2 + H3 + H6 + H7
A2 = H4 + H5 + H6 +H7
IDLE = (I0+I1+I2+I3+I4+I5+I6+I7)´

74x148 Priority Encoders

GS (Group Select) : asserted when the device is enabled (EI_L=0) and one or more of the request inputs are asserted
EO : asserted when EI_L is asserted but no request input is asserted
another lower-priority ‘148 may be enabled

74x148 Priority Encoders Logic diagram

2.2 Encoders in PLD

Logic diagram for a PLD-based 15-input priority encoder

3. Three-state devices

Various three-state buffers (or drivers)

(a) noninverting, active-high enable 
(b) noninverting, active-low enable
(c) inverting, active-high enable 
(d) inverting, active-low enable

Multiple sources can share a single party line
Only one device talks on the line at a time

3.1 Dead Time
- Typical three-state devices are designed so that tpLZ or tpHZ < tpZL or tpZH
->to avoid fightingwhen driven by two 3-state devices
-> but, delays and skews in control circuits may make the outputs still fight
- Design control logic guaranteeing dead time
-> safeway to use three-state devices to avoid fighting
-> during the dead time, no one is driving it

3.2 Standard SSI and MSI Three-State Buffers
; Several independent 3-state buffers may be packaged in a single SSI IC

Using 74x541 as a Microprocessor input port

74x245 octal 3-state transceiver

G_L = 0 & DIR = 0 → Data transfer from B to A
G_L = 0 & DIR = 1 → Data transfer from A to B

Bidirectional buses and Transceiver operation

Bidirectional buses and Transceiver operation

3.3 three state drivers VHDL code

VHDL program with four 8-bit three-state drivers

4. Multiplexers
Digital switch ; Connecting data from one of n sources to its output

Multiplexer structure

4.1 Standard MSI Multiplexers: 74x151 [8 input 1bit]

74x151 8x1 (8-input 1-bit output) multiplexer

4.2 Standard MSI Multiplexers: 74x157 [2 input 4bit]

74x157 2-input, 4-bit multiplexer

4.3 Standard MSI Multiplexers: 74x153 [4 input 2bit]

4.4 Standard MSI Multiplexers: 32-to-1 Mux

4.5 Multiplexers, Demultiplexers, and Buses

4.6 Binary Decoders Used as Demultiplexers

2-to-4 74x139 binary decoder used as 1-bit input, 4 output demultiplexer

4.7.1 Dataflow VHDL program for 4-input, 8-bit multiplexer

Dataflow VHDL program for 4-input, 8-bit multiplexer

4.7.2 Behavioral VHDL program for 4-input, 8-bit multiplexer

Behavioral VHDL program for 4-input, 8-bit multiplexer

출처 
1. Digital Design: Principles and Practices, Fourth Edition, John F. Wakerly

2. KOCW. 디지털시스템설계. 아주대학교. 양회석. http://www.kocw.net/home/search/kemView.do?kemId=1145013